1. Field of the Invention
The present invention relates to a microelectronic device chip including a hybrid Au bump, a package of the microelectronic device chip, a liquid crystal display (LCD) apparatus including the microelectronic device chip, and a method of fabricating the microelectronic device chip.
2. Description of the Related Art
With the rapid development of technology and the move towards portability, electronic devices such as cellular phones, personal data assistants (PDAs), flat display devices such as LCD devices, and notebook computers have been developed to be thin, light, and small. As a result, chips mounted in these electronic devices have been developed to be miniature. A conductive bump has been widely used as a means to connect chip packages to external electronic devices.
Recently, this conductive bump has been mainly formed using an electrolytic plating method involving a non-cyan series plating solution. A cyan series plating solution was used formerly; however, recently a non-cyan series plating solution has been mainly used. In the case where the conductive bump is formed using a non-cyan series plating solution including Na3Au(SO3)2 compared with the use of a cyan series plating solution including KAu(CN)2, a surface of the completed bump is not coarse but has a fine texture making it easy to perform a subsequent combining process. Further, since a noxious gas like HCN is not generated, environmental pollution can be reduced and a safer working environment can be achieved.
An electrical test, referred to as an electrical die sorting (EDS) test, is conducted on the microelectronic device formed on a wafer to check the quality of the chip. The EDS test is conducted by bringing a probe tip into contact with the conductive bump, which is electrically connected to the microelectronic device, and then transmitting an electrical signal to the microelectronic device through the probe tip.
In a case where the conductive bump is formed using the non-cyan series plating solution, foreign materials generated from the conductive bump adhere to the probe tip, thereby frequently generating errors in the electrical signal of the EDS test. The erroneous test results, in which normal chips were found to be short or open, is due to these foreign materials. Further, the foreign materials change the contact resistance between the probe tip and the conductive bump, thereby producing an erroneous test result.
To solve the above problems, whenever chip testing is performed, it is necessary to clean the probe tip. That is, after 20-50 chips are tested, the probe tip cleaning process must be performed. This results in abrasion of the probe tip which increases production costs. Further, EDS test time increases, thereby generating a drop in yield.